An audio formatter is a logical device that produces audio output and may have several components, for example, a speech component and multiple sound components. Multi-channel signal formatters are usually based on a single clock. A single clock may not work for systems, in which the signal formatters have to operate independently as well as in-phase. One option to overcome this problem may be to utilize a set of signal formatters based on a single clock and additional signal formatters may be utilized to run on separate clocks. The resultant outputs may be multiplexed. One problem with this option is that at least two extra signal formatters are required for operating in a 6-channel mode and at least three signal formatters are required for operating in an 8-channel mode.
FIG. 1 is a block diagram of an exemplary conventional multi-channel signal formatter system. Referring to FIG. 1, the system comprises three serial signal formatters 102, 104 and 106 and three multiplexers 108, 110 and 112. Each of the serial signal formatters 102, 104 and 106 are coupled to a system clock (SYS_CLK). The serial signal formatters 102, 104 and 106 may be adapted to send out a request signal (REQUEST_A, REQUEST_B or REQUEST_C) to an audio device and may receive an acknowledge signal (VALID_A, VALID_B or VALID_C) from the audio device. The data signals (DATA_A, DATA_B or DATA_C) may be input to the serial signal formatters 102, 104 and 106 on the system clock (SYS_CLK) domain.
The serial signal formatters 102, 104 and 106 may output a synchronous signal (SYNC_A, SYNC_B or SYNC_C), a clock signal (SCLK_A, SCLK_B or SCLK_C) and a data signal (SDAT_A, SDAT_B or SDAT_C). The data signals (SDAT_A, SDAT_B or SDAT_C) that are output from the serial signal formatters 102, 104 and 106 may run on one of many possible signal clock domains, for example, a MCLK domain. The multiplexers 108, 110 and 112 may be adapted to multiplex several MCLK signals (MCLK_0 . . . MCLK_n) from different audio devices and output a MCLK signal (MCLK_A, MCLK_B or MCLK_C) to each of the serial signal formatters 102, 104 and 106 respectively. The delay through each MCLK signal multiplexer 108, 110 and 112 may be different and the MCLK signal is asynchronous with the system clock signal SYS_CLK. The three multiplexers 108, 110 and 112 may be adapted to select at least one MCLK signal to clock the three serial signal formatters 102, 104 and 106 respectively.
FIG. 2 is a timing diagram illustrating a common serial signal format that may be utilized in connection with the conventional multi-channel signal formatter system of FIG. 1, for example. Referring to FIG. 2, there is shown signals MCLK 202, SCLK 204, SYNC 206 and SDAT 208. The signal MCLK 202 may be a high frequency clock signal that may be synchronous with the serial signal formatter output clock signal SCLK 204, but with an arbitrary phase. The SYNC 206 signal may be asserted on the first falling edge of the SCLK 204 signal and may remain high until the end of one cycle of operation, for example, the left channel in a 2-channel mode. The SDAT 208 output signal may send out a word of data on the rising edge of SYNC 206 signal with its most significant bit (MSB) aligned to the rising edge of the SYNC 206 signal, for example, during the left channel cycle in a 2-channel mode. The next word may be sent out by the SDAT 208 signal on the falling edge of SYNC 206 signal with its most significant bit (MSB) aligned to the falling edge of SYNC 206 signal, for example, during the right channel cycle in a 2-channel mode.
In one mode of operation, each output serial signal formatter 102, 104 and 106 (FIG. 1) may work independently in a 2-channel mode, wherein each serial signal formatter 102, 104 and 106 may supply its own synchronization signal SYNC 206, clock signal SCLK 204, and data signal SDAT 208. Other common serial signal formats may delay SDAT 208 signal by a clock or may align SDAT 208 signal with the least significant bit (LSB). Some serial signal formats may be adapted to invert the polarities of SYNC 206 signal and/or SCLK 204 signal.
Another mode of operation is to have the outputs of the three serial signal formatters 102, 104 and 106 (FIG. 1) in phase working together in a 6-channel mode. The serial signal formatters B 104 and C 106 may supply data signals DATA_A and DATA_B respectively, but only the SYNC 206 signal and SCLK 204 signal from the serial signal formatter A 102 may be used. Such an output may look like FIG. 2 above, except the SDAT 208 signal may be a 3-bit bus rather than a single bit-bus. Each serial signal formatter 102, 104 or 106 may be adapted to operate in both 2-channel and 6-channel modes. The output signals of the serial signal formatters 102, 104 and 106 may be clocked by the MCLK 202 signal, while the system clock signal SYS_CLK may clock the input of serial signal formatters 102, 104 and 106. To ensure that the output signals are in phase, both bit-by-bit and sample-by-sample a method is needed.
FIG. 3 is a timing diagram illustrating a problem that may occur during bit alignment in the conventional multi-channel signal formatter system of FIG. 1, for example. Referring to FIG. 3, there is shown an ALIGN 302 signal, MCLK_A 304 signal, ALIGN_A 306 signal, MCLK_B 308 signal and ALIGN_B 310 signal. The ALIGN 302 signal is the output of a flip-flop with its input signal as the system clock SYS_CLK. The MCLK_A 304 and MCLK_B 308 signals may be the outputs of signal sources A and B respectively. The ALIGN_A 306 and ALIGN_B 310 signals may be utilized to initialize bit counters. To ensure proper phase alignment of output signals in 6-channel mode, an ALIGN 302 signal may be transferred from the system clock domain to the MCLK domain. The ALIGN 302 signal may be utilized to initialize bit counters in each of the serial signal formatters 102, 104 and 106, which in turn may be adapted to control when each bit may be output. Referring to FIG. 3, a problem is illustrated that may occur when the ALIGN 302 signal is clocked independently with each MCLK signal. The serial signal formatters A 102 and B 104 (FIG. 1) may select the same MCLK source, but there may be a slight difference in delay in the MCLK multiplexers 108, 110 and 112 that may cause ALIGN_A 306 signal to just catch the rising edge of MCLK_A 304 signal, while ALIGN_B 310 signal may miss the rising edge of MCLK_B 308 signal that occurs in the same clock cycle. This may result in ALIGN_A 306 signal and ALIGN_B 310 signal being offset by one MCLK period and the resulting SDAT 208 output signal may be offset by one clock period.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.